د. محمدالجهاني

قسم هندسة الحاسوب كلية الهندسة

الاسم الكامل

د. محمد مفتاح محمد الجهاني

المؤهل العلمي

دكتوراة

الدرجة العلمية

محاضر

ملخص

تنزيل السيرة الذاتية

معلومات الاتصال

روابط التواصل

الإستشهادات

الكل منذ 2017
الإستشهادات
h-index
i10-index

المؤهلات

دكتوراة


5 ,2015

ماجستير


7 ,2014

ماجستير


12 ,2004

المنشورات

Front-end of Wake-Up-Word Speech Recognition System Design on FPGA (Dissertation)

A typical speech recognition system is push button operated (Push-to-talk), which requires hand movement and hence mixed multi-modal interface. However, for disabled patients and those who use hands-busy applications (e.g., where the user has objects to manipulate or device to control while asking for assistance from another device) movement may be restricted or impossible. The only alternative is to use Speech Only Interface. The method that is being proposed is called Wake-Up-Word Speech Recognition (WUW-SR). A WUW-SR system would allow the user to operate (activate) many systems (Cell phone, Computer, Elevator, etc.) with speech commands instead of hand movements. This work defines a new front-end paradigm of the Wake-Up-Word Speech Recognition on Field Programmable gate Arrays (FPGA). The-State-Of-The-Art Front-end of WUW-SR system is based on three different subsystems that produce three sets of features: (1) Mel-frequency Cepstral Coefficients (MFCC), (2) Linear Predictive Coding Coefficients (LPC), and (3) Enhanced Mel-frequency Cepstral Coefficients (ENH_MFCC). These extracted features are then compressed and transmitted to the server via a dedicated channel, where subsequently they are decoded. These features are decoded with corresponding Hidden Markov Models (HMMs) in the back-end stage of the WUW-SR. In the WUW-SR system, the front-end processor is located at the terminal (e.g. Mobile phone) which is typically connected over a data network to remote back-end recognition (e.g., server). WUW’s front-end can be added to any hand-held electronic device compatible with WUW-SR and command (activate) it by using our voice only (no push to talk as is presently done). WUW’s front-end is designed, and implemented in Altera DSP development kit with Cyclone III FPGA as a portable system acting as a processor that is capable of computing three different sets of features at a much faster rate than software. It is cost effective, consumes very little power, and it is not limited by having to operate on a general-purpose computer so it can be used on any portable device.
Mohamed Muftah Eljhani(2-2015)


Front-end of Wake-Up-Word Speech Recognition System Design on FPGA (Journal)

A typical speech recognition system is push button operated (Push-to-talk), which requires hand movement and hence mixed multi-modal interface. However, for disabled patients and those who use hands-busy applications (e.g., where the user has objects to manipulate or device to control while asking for assistance from another device) movement may be restricted or impossible. One alternative is to use Speech Only Interface. The method that is being proposed is called Wake-Up-Word Speech Recognition (WUW-SR). A WUW-SR system would allow the user to operate (activate) many systems (Cell phone, Computer, Elevator, etc.) with speech commands instead of hand movements. This paper introduces a new front-end paradigm of the Wake-Up-Word Speech Recognition. The state of the art WUW-SR system is based on three different sets of features. We present an experimental FPGA design and implementation of a novel architecture of a real time feature extraction processor that generates MFCC, LPC, and ENH_MFCC features simultaneously. In the WUW-SR system, the recognizer front-end is located at the terminal which is typically connected over a data network to remote back-end recognition (e.g., server). The three sets of feature extraction of speech are performed at the front-end. These extracted features are then compressed and transmitted to the server via a dedicated channel, where subsequently they are decoded. Our front-end can be added to any hand-held electronic device compatible with WUW-SR and command (activate) it by using our voice only (no push to talk as is presently done). Our front-end is designed, simulated and implemented in Altera DSP development kit with Cyclone III FPGA as a portable system acting as a processor that is capable of computing three different sets of features at a much faster rate than software. It is cost effective, consumes very little power, and it is not limited by having to operate on a general-purpose computer and used on any portable device.
Mohamed Muftah Eljhani(7-2013)
Publisher's website


Wake-Up-Word Feature Extraction on FPGA (Journal)

Wake-Up-Word Speech Recognition task (WUW-SR) is a computationally very demand, particu-larly the stage of feature extraction which is decoded with corresponding Hidden Markov Models (HMMs) in the back-end stage of the WUW-SR. The state of the art WUW-SR system is based on three different sets of features: Mel-Frequency Cepstral Coefficients (MFCC), Linear Predictive Coding Coefficients (LPC), and Enhanced Mel-Frequency Cepstral Coefficients (ENH_MFCC). In (front-end of Wake-Up-Word Speech Recognition System Design on FPGA) [1], we presented an experimental FPGA design and implementation of a novel architecture of a real-time spectrogram extraction processor that generates MFCC, LPC, and ENH_MFCC spectrograms simultaneously. In this paper, the details of converting the three sets of spectrograms 1) Mel-Frequency Cepstral Coefficients (MFCC), 2) Linear Predictive Coding Coefficients (LPC), and 3) Enhanced Mel-Frequency Cepstral Coefficients (ENH_MFCC) to their equivalent features are presented. In the WUW- SR system, the recognizer’s front-end is located at the terminal which is typically connected over a data network to remote back-end recognition (e.g., server). The WUW-SR is shown in Figure 1. The three sets of speech features are extracted at the front-end. These extracted features are then compressed and transmitted to the server via a dedicated channel, where subsequently they are decoded.
Mohamed Muftah Eljhani(1-2014)
Publisher's website


Voice Activity Detector of Wake-Up-Word Speech Recognition System Design on FPGA (Journal)

A typical speech recognition system is push-to-talk operated that requires activation. However for those who use hands-busy applications, movement may by restricted or impossible. One alternative is to use Speech-Only Interface. The proposed method that is called Wake-Up-Word Speech Recognition (WUW-SR) that utilizes speech only interface. A WUW-SR system would allow the user to activate systems (Cell phone, Computer, etc.) with only speech commands instead of manual activation. The trend in WUW-SR hardware design is towards implementing a complete system on a single chip intended for various applications. This paper presents an experimental FPGA design and implementation of a novel architecture of a real time feature extraction processor that includes: Voice Activity Detector (VAD), and features extraction, MFCC, LPC, and ENH_MFCC. In the WUW-SR system, the recognizer front-end with VAD is located at the terminal which is typically connected over a data network(e.g., server)for remote back-end recognition. VAD is responsible for segmenting the signal into speech-like and non-speech-like segments. For any given frame VAD reports one of two possible states: VAD_ON or VAD_OFF. The back-end is then responsible to score the features that are being segmented during VAD_ON stage. The most important characteristic of the presented design is that it should guarantee virtually 100% correct rejection for non-WUW (out of vocabulary words - OOV) while maintaining correct acceptance rate of 99.9% or higher (in vocabulary words - INV). This requirement sets apart WUW-SR from other speech recognition tasks because no existing system can guarantee 100% reliability by any measure.
Mohamed Muftah Eljhani(12-2014)
Publisher's website


Reduced Instruction Set Computer Design on FPGA (Conference)

The main purpose of this paper is to design, verify and implement 16_bit RISC (Reduced Instruction Set Computer) processor that can be used for many embedded applications. The basic modules of this processor are programmed and simulated using Verilog HDL (Hardware Description Language), and implemented on Cyclone IV FPGA (Field Programmable Gate Arrays). Compared with general CPU it is not merely simplified the instruction set system but also make the computer structure simpler and more rational through simplifying the instruction system. Thus, the operating speed is highly improved. RISC adopts hardwire logic instead of micro-program control to realize its sequential control signals. The speed of control sequence generated is much faster than using micro-program control because it has saved the time of fetching microinstruction. The philosophy of RISC design presented here favors a smaller and simpler set of instructions. Those instructions take the same amount of time to execute. The philosophy of our design architecture was to keep the instruction set very simple. This in turn implies that addressing modes supported by instruction set a further streamlined compared to CISC (Complex Instruction Set Computer) architectures. Avoiding such addressing modes must be kept to minimum, which leads to the instructions that can be executed effectively in eight clock cycles.
Mohamed Muftah Eljhani(6-2021)
Publisher's website


An Alternative Microprocessor Bus Structure Design on FPGA (Journal)

A tri-state-based bus implementation is useful for any large design application with a large number of design blocks, but at the same time, it can complicate synchronization and testing. Field programmable gate array (FPGA) chips do not have enough tristate drivers to mount large buses. Alternatively, designers can use bus structures based on multiplexers. In this research paper, the basic modules of the proposed microprocessor bus system are designed, implemented, and simulated using Verilog hardware description language (HDL), and implemented and routed to the FPGA. Microprocessors with a tristate-based bus compared to a bus system with a multiplexer bus have proven to consume more power, and have less timing and test process flexibility. The proposed multiplexed bus architecture can be used for embedded systems and mobile electronic devices that require high speed and low power consumption. In the intellectual property (IP) integration has limited tristate-based buses, so large design applications can use multiplexer-based buses. Application-specific integrated circuit designs use an internal multiplexer-based bus for the same reason. Also, a tristate-based bus has timing and power consumption issues due to the capacitive load of the nodes.
Mohamed Muftah Eljhani(9-2022)
Publisher's website


University of Tripoli’s Real-Time Density-Based Traffic Light Controller on FPGA (Journal)

The university of Tripoli encounters today’s mobility challenges such as increased traffic and congestion. This paper presents a real-time density-based traffic light controller system. The system ensures saving time for faculties, students, and employees by reducing congestion within the university campus. Real-time traffic density is detected using an array of display screens and infrared (IR) sensors placed on each four-way intersection. The display screens provide information on road congestion to show the right way to enter or exit the campus. The system continues monitoring the data coming from display screens and IR sensors and provides real-time traffic. in case of emergencies, the system gives the priority to emergency vehicles using radio frequency identification (RFID). In this research work, the basic modules of the proposed real-time density-based traffic light controller system are designed and simulated with Verilog Hardware Description Language (HDL) and implemented on Cyclone IV GX field-programmable gate arrays (FPGA). This design will contribute to the stabilization and optimization of the traffic at the University of Tripoli campus.
Mohamed Muftah Eljhani(9-2022)