Roles

Dr. Eljhani is faculty member with a demonstrated history of working in the higher education. Skilled in the area of high level synthesis of advanced digital systems and digital integrated circuit design with FPGA using Verilog Hardware Description Language, for more than 25 years both in the academics and industries. Now teaching Computer Engineering courses at Department of Computer Engineering, University of Tripoli. Strong education professional with a Ph.D. focused in Computer Engineering from Florida Institute of Technology, a M.Sc. focused in Computer Sciences from Florida Institute of Technology, and a M.Sc. focused in Computer Engineering from Beijing University of Aeronautics & Astronautics. 

Careers

·         Full time faculty member at department of Computer Engineering, University of Tripoli

·         Former head of study and examinations department at college of engineering, University of Tripoli

Research Interests

Dr. Eljhani doctoral dissertation topic in the area of natural speech processing relates to designing and implementing Front-end of Wake-Up-Word Speech Recognition System (WUW-SR) on FPGA. The developed work relates to a new front-end paradigm named WUW-SR. The State-of-the-art WUW-SR enables users to activate systems (e.g., handheld devices) with speech command (e.g., Wake-Up-Word) instead of using other paradigms for activation (e.g., push to talk). He developed a new front-end paradigm on FPGA that presently is not widely recognized. The state-of-the-art WUW_SR system is based on three different sets of features: Mel-frequency Cepstral Coefficients (MFCC), Linear Predictive Coding Coefficients (LPC), and Enhanced Mel-frequency Cepstral Coefficients (ENH-MFCC). These features were needed to improve the accuracy of the system by combining the individual scores. Those scores were obtained with corresponding Hidden Markov Models (HMMs) as back-end stage of the WUW-SR. Presented experimental design and implementation of a novel architecture of a real time feature extraction processor that generates those features simultaneously was the topic of my dissertation. The WUW_SR is designed and implemented in Altera DSP development kit with Cyclone III FPGA as a portable system acting as a processor that is capable of computing three different sets of feature at very fast rate. It is cost effective solution that consumes very little power, and it is not limited by having to operate on a general-purpose computer. This solution hence, is suitable to be used on any portable device. Also he has published several research journal papers in the area of high level synthesis of advanced digital systems, and embedded Systems design with Field-Programmable Gate Arrays (FPGA) using Hardware Description Language.

External Activities

Participate in scientific conferences, reviews and evaluation of scientific research.

Supervise a research center for integrated digital systems