Abstract
The increasing complexity of System-On-Programmable-Chip (SoPC) designs has led to significant challenges in design productivity. The instantiation and interface design of SoPCs significantly impact system performance and power consumption. This paper provides an overview of prevalent digital system buses, explores various bus architectures, and introduces a novel bus architecture. Additionally, it introduces a bus controller facilitating data path module transactions. Implementing tri-state-based bus architecture is beneficial for extensive designs with numerous blocks. However, due to limitations in Field Programmable Gate Array (FPGA) chips regarding tristate drivers for large buses, a new multiplexer-based bus structure and controller are proposed. This research involves designing, implementing, and simulating fundamental modules of the multiplexer-based bus system using Verilog hardware description language. Subsequently, comparisons with the tri-state-based bus system demonstrate that the multiplexer-based bus achieves higher speed, lower power dissipation, enhanced flexibility in timing, and improved testing capabilities. The proposed bus architecture is suitable for FPGAs and other programmable chips requiring a high-speed, low-power bus. In SoPC design, multiplexer-based buses are favoured due to easier Intellectual Property integration compared to tri-state-based buses. Moreover, application-specific integrated circuits prefer internal multiplexer-based buses due to the timing and power consumption challenges associated with tri-state-based buses caused by capacitive loads on their nodes.