Abstract
—The expanding complexity of the System-on-Programmable-Chip (SOPC) has driven to the basic “design productivity gap” issues. SOPC design instantiation and interface encompasses a critical effect on system execution time and power dissipation. This paper overviews existing digital system buses which are commonly used in SOPC systems, discusses different bus architectures, and introduces a new bus architecture. Also, we present the design of bus controller which handles the transactions between data path modules. Tri-state-based bus implementation is useful for very large design applications with large number of blocks. Field Programmable Gate Arrays (FPGA) chips don’t contain a sufficient number of tristate drivers to implement a system with large buses, the alternative we proposed a new multiplexer-based bus structure and bus controller. In this research work the basic modules of the proposed multiplexerbased bus system is designed, implemented, and simulated with verilog hardware description language (HDL), and placed and routed to Cyclone IV GX FPGA, and then compared with tristate-based bus system and proved that the multiplexer-based bus is faster and has less power dissipation, additionally it is more flexible for timing and testing process. The proposed bus architecture can be used in FPGA and other programmable chips that needs high speed bus with low power consumption. In the SOPC design, most design applications use multiplexer based bus, because Intellectual Property (IP) integration is easier than tri-state-based bus. Also, in the application specific integrated circuit (ASIC) design uses internal multiplexer based bus because tri-state-based bus has issues with timing and power consumption due to the capacitive load by its nodes.