Evaluation of System-on-Chip Interconnect Architectures: A Case study of Fat-tree Interconnection Networks

تاريخ النشر


نوع المقالة

رسالة ماجستير

عنوان الرسالة

كلية العلوم - جامغة طرابلس


أسماء شعبان العصار



In practice, most SoCs are multiprocessor systems-on-chips (MPSoCs) because it is too difficult to design a complex system-on-chip without making use of multiple CPUs. MPSoCs are the latest picture of very large scale integration (VLSI) technology. The architecture of the system is generally tailored to the application rather than being a general-purpose chip. This in turn enforces designers to move beyond logic design into advanced computer architecture and parallel processing. In such architectures, cores are integrated via a custom or commercial interconnection network with a controller, timing and a function interface to the external world. Current state-of-the-art SoCs already embeds typical sub-systems such as digital signal processors (DSP), RAM, ROM, MPEG cores.The main goal of this thesis is to design an efficient switch for Fat-tree interconnection networks. In addition a useful survey study for interconnection networks architectures, technologies and routing algorithms was provided. The survey included in some details commonly used switching methods and virtual channel arrangements. The proposed switch structure has been validated by a software model.A set of algorithms and procedures have been developed to facilitate the switch functionality. Those procedures include the control of transmission of the packets from switch input buffer to switch output buffer and transferring packets from switch output buffer to neighboring switch input buffer. While the input/output link controllers take care of buffer assignments to flits (packet) and deals with buffer organization. More over, the algorithms include (i) the routing algorithm which is the least common ancestor routing algorithm, (ii) arbitration algorithm that based on round-robin technique.Therefore in this thesis we have proved the correctness of the functionality of the proposed switch in software model that have been written in C++ language. The obtained simulation results of the switch functionality in fat-tree of 16 nodes definitely declare the correctness of the proposed arbitration scheme as well as showing the efficiency of the routing algorithm. Finally, we can say that the fat-tree interconnection network is very good candidate to implement future NoC connectivity for current and future multiprocessor systems-on-chips (MPSoCs) designs due to its modular, flexible and regular structured design. In turn, these features are suitable as well for VLSI realizations.