Evaluations of Fat Tree Based System on Chip Interconnection Architectures

Date

2009-12

Type

Conference paper

Conference title

In Proc. of the 15th Int. IP/ESC 09 Conference, Grenoble, France, December 2009.

Issue

Vol. 1 No. 1

Author(s)

Azeddien M S Sllame
Asma Alasar

Pages

30 - 35

Abstract

In this paper we describe NOC FAT-Tree Based SOC Interconnection Architecture. The proposed internal switch structure contains the following essential items; router, input link controller unit, output link controller, virtual channels. Simulator in C++ was developed. Preliminary results are encouraging and declared that it can be used efficiently in evaluating SOC interconnection flow control, utilization of virtual channels, and can use different routing algorithms and arbitrations for comparison purposes.

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